Researchers at King Abdullah University of Science and Technology (KAUST) in Saudi Arabia have achieved a major milestone in microchip design: they successfully created the world’s first six-layer (six-stack) hybrid CMOS microchip for large-area electronics.
This breakthrough, published in Nature Electronics, shatters the previous record of just two stacked layers, setting a new benchmark for how efficiently and compactly future electronics can be built.
CMOS, short for complementary metal-oxide semiconductor, is the foundation of most modern electronics—from smartphones and laptops to satellites and medical equipment.
Traditional silicon-based CMOS chips have been continuously shrinking for decades to pack more computing power into smaller devices.
But as components reach atomic scales, engineers face the limits of physics—making it increasingly difficult and expensive to keep reducing their size.
“The semiconductor industry has long relied on making transistors smaller to boost performance,” explained Associate Professor Xiaohang Li, who led the study and directs the KAUST Advanced Semiconductor Laboratory.
“But we’re now approaching quantum limits. To keep advancing, we need a new direction—stacking transistors vertically instead of shrinking them horizontally.”
This vertical stacking approach effectively creates a “skyscraper” of transistors, allowing more computing power to fit into the same footprint.
However, building these multi-layered chips has been extremely challenging.
Conventional fabrication methods require very high temperatures—often above 400°C—which can damage lower layers when new ones are added.
The KAUST team overcame this by developing a low-temperature fabrication process that never exceeds 150°C, and in many steps, operates near room temperature. This gentle process preserves the integrity of the lower layers while maintaining electrical performance.
The researchers also made key improvements to ensure each new layer remains smooth and precisely aligned, both of which are essential for the vertical connections between transistors.
“Microchip design is all about packing more power into less space,” said postdoctoral researcher Saravanan Yuvaraja, the paper’s first author.
“By refining each fabrication step, we’ve created a clear roadmap for building taller, more efficient semiconductor stacks.”
This achievement could have far-reaching implications for emerging technologies like flexible electronics, wearable health devices, and the Internet of Things (IoT)—where lightweight, low-cost, and high-performance chips are in demand.
With this six-stack hybrid CMOS chip, the KAUST team has not only broken a world record but also opened a new frontier for the future of electronic miniaturization and performance.
Source: KSR.
