Engineers have developed an exciting new technology that could revolutionize the way computer chips are made, enabling faster and more efficient AI systems.
As the electronics industry hits the limit of how many transistors can fit on a chip, researchers are turning to a new approach—building chips upward instead of outward.
This idea, similar to replacing a single-story house with a skyscraper, involves stacking layers of transistors and semiconducting materials on top of each other.
Such multilayered chips can process much more data and perform complex functions, paving the way for advanced AI hardware.
Currently, chips are built on silicon wafers, which act as their base. However, silicon wafers are thick and bulky, slowing down communication between layers.
To address this, engineers at MIT have developed a new method that eliminates the need for silicon wafers altogether. This innovation allows chip layers to be in closer contact, enabling faster and more efficient data transfer.
In their study, published in the journal Nature, the researchers stacked layers of high-quality semiconducting materials directly on top of each other.
These materials are known as transition-metal dichalcogenides (TMDs), a promising alternative to silicon. Unlike silicon, TMDs maintain their performance even at extremely small scales, making them ideal for modern transistors.
The researchers overcame a major challenge: how to build these stacked layers at low temperatures.
High temperatures, above 400 degrees Celsius, can damage the delicate circuitry of underlying layers. By borrowing techniques from metallurgy, the science of metals, they found a way to grow TMD materials at just 380 degrees Celsius.
Their method uses a mask with tiny openings, or “pockets,” to guide the growth of semiconducting materials. By starting the growth process at the edges of these pockets, where it requires less heat, the team successfully created single-crystalline layers at lower temperatures.
Using this technique, they built a multilayered chip with alternating layers of two TMDs: molybdenum disulfide (for n-type transistors) and tungsten diselenide (for p-type transistors). These transistors are the building blocks for all logic operations in electronic devices.
This new chip design eliminates the need for thick silicon wafers between layers, which are used in conventional 3D chips. Instead, the stacked layers can communicate directly, improving speed and efficiency.
“This breakthrough opens up enormous potential for the semiconductor industry,” says Jeehwan Kim, associate professor of mechanical engineering at MIT and lead researcher. “It could lead to massive improvements in computing power for AI, logic, and memory applications.”
The new method could double the density of a chip’s components, making it possible to stack tens or even hundreds of layers. This innovation not only creates 3D logic chips but also combines memory and logic layers in a way that conventional methods cannot.
The researchers are now working on scaling up this technology to create full-scale AI chips. Kim has also launched a company, FS2 (Future Semiconductor 2D Materials), to commercialize the design.
“Our next step is to demonstrate professional AI chip operation at a larger scale,” Kim says.
If successful, this technology could power AI hardware for laptops, wearable devices, and more. It promises faster performance and greater storage capacity, rivaling the power of today’s supercomputers—all in a smaller, more efficient package.
This groundbreaking innovation has the potential to transform the semiconductor industry and unlock new possibilities for AI, making it faster, smarter, and more accessible than ever.
