High-performance silicon transistors can have gate channel lengths as short as 5 nanometers before source-drain tunneling. However, the loss of electrostatic control can lead to unacceptable leakage current when the device is off.
Now researchers use MoS2 (molybdenum disulfide) as a gate material to develop a transistor with a 1-nanometer physical gate. This is the smallest transistor reported to date. The finding is newly published in Science.
Researchers from University of California, Berkeley, University of Texas at Dallas, and Stanford University conducted the study.
They found that scaling of silicon (Si) transistors often could fail below 5-nanometer gate lengths because of severe short channel effects.
As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass.
Researchers used carbon nanotubes and MoS2, a component of blends and composites that require low friction. MoS2 is also used for applications in LEDs, lasers, nanoscale transistors, solar cells, and so on.
In the study, a transistor with a 1-nm physical gate was constructed with a MoS2 bilayer gate and a single-walled carbon nanotube gate electrode.
Researchers find that the ultrashort devices exhibited excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106.
In addition, simulations showed an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.
Researchers suggest that this finding support the view that density of transistors on integrated circuits will double every two years. The advance can increase performance of laptops, smartphones, televisions, and other electronics.
Citation: Desai SB, et al. MoS2 transistors with 1-nanometer gate lengths. Science, 354: 99-102. DOI: 10.1126/science.aah4698.
Figure legend: This Knowridge.com image is credited to Sujay Desai/Berkeley Lab.